Código fuente de diseño de bucle de bloqueo de fase digital basado en Verilog

inclk0,

c0,

c1);

entrada inclk0;

salida c0 ;

salida c1;

cable [5:0] sub_wire0;

cable[0:0] sub_wire5 = 1'h0;

cable[ 0:0] sub_wire5 = 1'h0;

cable[1:1] sub_wire2 = sub_wire0[1:

cable [0:0] sub_wire1 = sub_wire0[0:0]

cable c0 = sub_wire1;

cable c1 = sub_wire2;

cable sub_wire3 = inclk0; ] sub_wire4 = {sub_wire5, sub_wire3};

altpll altpll_ componente (

.inclk (sub_wire4),

.clk (sub_wire0),

.activeclock(),

.areset (1'b0),

.clkbad(),

.clkena ({6{1' b1}}),

.clkloss (),

.clkswitch (1'b0),

.configupdate (1'b0),

.enable0 (),

.enable1 (),

.extclk (),

.extclkena ({4{1'b1. }}),

.fbin (1'b1),

.fbmimicbidir (),

.fbout (),

.locked(),

.pfdena ​​​​(1 'b1),

.phasecounterselect ({4{1'b1}}),

. fasehecha ( ),

.phasestep (1'b1),

.phaseupdown (1'b1),

.pllena (1' b1),

.scanclr (1'b0),

.scanclk (1'b0),

.scanclkena (1'b1),

.scandata (1'b0),

.scandataout (),

.scandone (),

.scanread (1'b0),

.scanwrite (1'b0),

.sclkout0 (),

.sclkout1 (),

.vcooverrange (),

.vcounderrange ());

defparam

altpll_component.clk0_divide_by = 1,

altpll_component.clk0_duty_cycle = 50,

altpll_componente.intendente_familia_dispositivo

= "Ciclón II",

altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",

altpll_component.lpm_type = "altpll",

altpll_component.operation_mode = "NORMAL",

altpll_component.port_activeclock = "PORT_UNUSED",

altpll_component.port_reset = "PORT_UNUSEDport_configupdate = "PORT_UNUSED",

altpll_component.port_fbin = "PORT_UNUSED",

altpll_component.port_inclk0 = "PORT_USED",

altpll_component.port_inclk1 = "PORT_UNUSED",

altpll_component.port_locked = "PORT_UNUSED",

altpll_component .port_phaseupdown = "PORT_UNUSED",

altpll_component.port_scanclr = "PORT_UNUSED",

altpll_component.port_scanclk = "PORT_UNUSED",

altpll_component.port_scanclkena = "PORT_UNUSED ",

altpll_component.port_scandata = "PORT_UNUSED",

altpll_component.port_scandone = "PORT_UNUSED",

altpll_component.port_scanread = "PORT_UNUSED",

altpll_component.port_scanwrite = "PORT_UNUSED",

altpll_component.port_clk0 = "PORT_UNUSED",

altpll_component.port_clk0 = "PORT_UNUSED",